Method of manufacturing a semiconductor memory device having capacitor electrodes and a vertical contact plug
AssigneeSK hynix Inc.
InventorNam Jae Lee
Life of this patent
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Abstract
A semiconductor memory device, and a method of manufacturing the same, includes: a gate stack structure including interlayer insulating layers and conductive patterns stacked in a first direction; a channel structure penetrating the gate stack structure; a peripheral contact plug spaced apart from the gate stack structure on a plane intersecting the channel structure, the peripheral contact plug extending in the first direction; and a capacitor spaced apart from the gate stack structure and the peripheral contact plug on the plane, the capacitor having an area wider than an area of the peripheral contact plug.
Claims8
A method of manufacturing a semiconductor memory device, the method comprising:
- forming a lower insulating layer in which an interconnection pattern and a lower conductive pattern are embedded;
- forming a stack structure over the lower insulating layer, the stack structure including interlayer insulating layers and sacrificial insulating layers alternately stacked in a first direction;
- forming a first opening and a second opening to penetrate the stack structure and the lower insulating layer and expose the lower conductive pattern;
- forming a conductive material in the first and second openings, wherein a thickness of the conductive material is controlled to fill the second opening and to open a central region of the first opening;
- separating the conductive material into a first capacitor electrode on a surface of the first opening and a vertical contact plug filling the second opening;
- forming a dielectric layer over a surface of the first capacitor electrode;
- and
- forming a second capacitor electrode over the dielectric layer to fill the first opening.
A method of manufacturing a semiconductor memory device, the method comprising:
- forming a lower insulating layer in which an interconnection pattern and a lower conductive pattern are embedded;
- forming a stack structure over the lower insulating layer, the stack structure including interlayer insulating layers and sacrificial insulating layers alternately stacked in a first direction;
- forming a first opening and a second opening to penetrate the stack structure and the lower insulating layer and expose the lower conductive pattern;
- forming a first capacitor electrode on a surface of the first opening;
- forming a dielectric layer over a surface of the first capacitor electrode;
- and
- forming a second capacitor electrode over the dielectric layer to fill the first opening,
- wherein the second opening is filled with a vertical contact plug while the first capacitor electrode is formed,
- wherein the dielectric layer extends to cover the vertical contact plug, and
- wherein the method further comprises, before the second capacitor electrode is formed, forming a contact hole penetrating the dielectric layer and exposing the vertical contact plug.
A method of manufacturing a semiconductor memory device, the method comprising:
- forming a lower insulating layer in which an interconnection pattern and a lower conductive pattern are embedded;
- forming a semiconductor structure over the lower insulating layer;
- forming first and second insulating patterns penetrating the semiconductor structure and overlapping the lower conductive pattern;
- forming a stack structure over the lower insulating layer, the stack structure including interlayer insulating layers and sacrificial insulating layers alternately stacked in a first direction;
- forming a first opening and a second opening to penetrate the stack structure and the lower insulating layer and expose the lower conductive pattern;
- forming a first capacitor electrode on a surface of the first opening;
- forming a dielectric layer over a surface of the first capacitor electrode;
- and
- forming a second capacitor electrode over the dielectric layer to fill the first opening,
- wherein the second opening is filled with a vertical contact plug while the first capacitor electrode is formed.
Dependencies are inferred from the claim text.