Semiconductor device for reducing concentration of thermal stress acting on bonding layers

A semiconductor device comprising:

• a wiring layer;
• a plurality of bonding layers arranged on the wiring layer and having conductivity;
• a semiconductor element having a rear surface facing the wiring layer and a plurality of pads provided on the rear surface, and bonded to the wiring layer via the plurality of bonding layers;
• one or more terminals connected to the wiring layer;
• and
• an insulating layer that is located on a side opposite to the semiconductor element with respect to the wiring layer in a thickness direction, and has a main surface, a rear surface, and a side surface between the main surface and the rear surface of the insulating layer,
• wherein the main surface of the insulating layer and the rear surface of the insulating layer face opposite sides in the thickness direction and the main surface of the insulating layer faces the rear surface of the semiconductor element,
• wherein the plurality of bonding layers are arranged in a grid shape when viewed along the thickness direction,
• wherein each of the plurality of pads is electrically connected to a circuit formed inside the semiconductor element and any of the plurality of bonding layers,
• wherein at least one of the plurality of pads is located to be spaced apart from the plurality of bonding layers when viewed along the thickness direction,
• wherein the plurality of bonding layers overlaps the semiconductor element when viewed along the thickness direction,
• wherein the semiconductor element includes an insulating film, which is arranged on the rear surface of the semiconductor element and exposes a portion of each of the plurality of pads, and a rewiring provided on the insulating film,
• wherein the rewiring includes:
• a plurality of bump layers, each of which is bonded to the wiring layer via any of the plurality of bonding layers;
• and
• a main body layer connected to at least one of the plurality of pads, and formed to extend to be in contact with the insulating film and to be connected to at least one of the plurality of bump layers,
• wherein the semiconductor element includes a dummy pad provided on the insulating film and electrically insulated from the circuit,
• wherein the dummy pad is bonded to the wiring layer via any of the plurality of bonding layers,
• wherein the plurality of bonding layers is arranged at equal intervals,
• wherein the plurality of bump layers is disposed not to overlap the plurality of pads when viewed along the thickness direction,
• wherein each of the one or more terminals is configured to cover a portion of the side surface of the insulating layer and a portion of the rear surface of the insulating layer,
• wherein each of the one or more terminals is formed to protrude from the rear surface of the insulating layer in the thickness direction,
• wherein the wiring layer has a plurality of base portions, each of the plurality of base portions faces a side opposite to the main surface in the thickness direction and has a bottom surface exposed from any of a plurality of penetrating portions of the insulating layer penetrating from the main surface in the thickness direction,
• wherein each of the plurality of base portions has a side surface that is connected to a bottom surface of any of the plurality of base portions and faces a direction orthogonal to the thickness direction, the side surface of each of the plurality of base portions includes an exposed portion exposed from any of the plurality of penetrating portions, and
• wherein each of the one or more terminals has a bottom portion that covers the bottom surface of any of the plurality of base portions, and a side portion that covers the exposed portion of the side surface of any of the plurality of base portions, which is connected to the bottom portion.