High breakdown voltage inter-metal dielectric layer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJoung-Wei Liou, Chin Kun Lan
Life of this patent
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Abstract
The present disclosure relates to a method of forming a semiconductor structure. The method includes depositing an etch-stop layer (ESL) over a first dielectric layer. The ESL layer deposition can include: flowing a first precursor over the first dielectric layer; purging at least a portion of the first precursor; flowing a second precursor over the first dielectric layer to form a sublayer of the ESL layer; and purging at least a portion of the second precursor. The method can further include depositing a second dielectric layer on the ESL layer and forming a via in the second dielectric layer and through the ESL layer.
Claims20
A method of forming a semiconductor structure, comprising:
- depositing an etch stop layer (ESL) over a first dielectric layer, wherein the depositing comprises:
- performing, on the first dielectric layer, a first plasma treatment process comprising an ammonia-based plasma process;
- performing a deposition cycle to form a first sublayer of the ESL, comprising:
- flowing a first precursor over the plasma-treated first dielectric layer, wherein the first precursor comprises aluminum;
- purging at least a portion of the first precursor;
- flowing a second precursor over the plasma-treated first dielectric layer to form the first sublayer of the ESL;
- and
- purging at least a portion of the second precursor;
- performing a second deposition cycle to form a second sublayer of the ESL on the first sublayer of the ESL;
- and
- performing a second plasma treatment process on the first sublayer of the ESL prior to performing the second deposition cycle, wherein the second plasma treatment process comprises an oxygen-based plasma process;
- depositing a second dielectric layer on the ESL;
- and
- forming a via in the second dielectric layer and through the ESL.
A method of forming a semiconductor structure, comprising:
- forming a conductive structure in a first dielectric layer;
- performing, on the first dielectric layer, a first plasma treatment process comprising an ammonia-based plasma process;
- depositing a second dielectric layer over the first dielectric layer, wherein the depositing comprises depositing an aluminum oxide layer with an oxygen to aluminum atomic ratio of about 1.2 to about 2.3 by:
- flowing a first precursor over the first dielectric layer;
- removing at least a portion of the first precursor;
- flowing a second precursor over the first dielectric layer;
- removing at least a portion of the second precursor;
- and
- performing a second plasma treatment process on the second dielectric layer;
- depositing a third dielectric layer on the second dielectric layer;
- and
- forming a via in the third dielectric layer and through the second dielectric layer.
A method of forming a semiconductor interconnect structure, comprising:
- depositing a first dielectric layer in a deposition chamber;
- forming a plurality of metal structures in the first dielectric layer;
- performing a first plasma treatment on the first dielectric layer and the plurality of metal structures in the deposition chamber;
- forming an etch stop layer with an aluminum content of about 30% to about 45%, an oxygen content of about 55% to about 70%, and a hydrogen content of about 0.5% to about 3% on the first dielectric layer, comprising:
- flowing a trimethylaluminum (TMA) precursor over the first dielectric layer;
- purging at least a portion of the TMA precursor, wherein the purging comprises flowing a first inert gas into the deposition chamber;
- flowing a second precursor into the deposition chamber, wherein the second precursor is configured to react with dangling bonds of the TMA precursor;
- and
- purging at least a portion of the second precursor, wherein the purging comprises flowing a second inert gas into the deposition chamber;
- performing a second plasma treatment on the etch stop layer;
- and
- depositing a second dielectric layer on the etch stop layer.
Dependencies are inferred from the claim text.