Method for manufacturing semiconductor memory having reduced interference between bit lines and word lines

A method for manufacturing a flash memory device, comprising:

• providing a substrate structure including a substrate and a plurality of gate structures on the substrate, the substrate including a plurality of active regions and a plurality of first isolation regions alternately arranged in a first direction and extending in a second direction different from the first direction, the plurality of gate structures being spaced apart from each other in the second direction and extending in the first direction, and each of the plurality of gate structures including a tunneling dielectric layer on an active region, a floating gate on the tunneling dielectric layer, an inter-gate dielectric layer on the floating gate, and a control gate on the inter-gate dielectric layer;
• forming an overhang surrounding an upper portion of the plurality of gate structures to form a gap structure between the plurality of gate structures;
• forming a second isolation region filling an upper portion of the gap structure and leaving a first air gap between the plurality of gate structures;
• removing the overhang and a portion of the second isolation region to expose a portion of the control gate;
• and
• forming a metal layer on the exposed portion of the control gate to form a metal silicide.

A method for manufacturing a flash memory device, comprising:

• providing a substrate structure including a substrate and a plurality of gate structures on the substrate, the substrate including a plurality of active regions and a plurality of first isolation regions alternately arranged in a first direction and extending in a second direction different from the first direction, the plurality of gate structures being spaced apart from each other in the second direction and extending in the first direction;
• forming an overhang surrounding an upper portion of the plurality of gate structures to form a gap structure between the plurality of gate structures;
• forming a second isolation region filling an upper portion of the gap structure and leaving a first air gap between the plurality of gate structures;
• and
• after forming the overhang surrounding an upper portion of the gate structures, removing a portion of the first isolation regions to form a second air gap between adjacent active regions.