Memory device with failed main bank repair using redundant bank
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsQiang Tang, Sangoh Lim
Life of this patent
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AssigneeYangtze Memory Technologies Co., Ltd.
InventorsQiang Tang, Sangoh Lim
Estimating the term…
In certain aspects, a memory device includes an array of memory cells, an input/output (I/O) circuit, and I/O control logic coupled to the I/O circuit. The array of memory cells includes a first-level memory unit which includes a plurality of second-level memory units. Each second-level memory unit includes N main banks and a redundant bank, where N is a positive integer. The I/O circuit is configured to direct N pieces of data to or from N working banks in a corresponding second-level memory unit. The I/O control logic is configured to determine the N working banks from the N main banks and the redundant bank in the corresponding second-level memory unit based on bank fail information indicative of a failed main bank of the N main banks and control the I/O circuit to direct the N pieces of data to or from the N working banks, respectively.
A memory device, comprising:
A system, comprising:
A method for operating a memory device comprising an array of memory cells, the array of memory cells comprising a first-level memory unit, the first-level memory unit comprising a plurality of second-level memory units, each second-level memory unit comprising N main banks and a redundant bank, where N is a positive integer, the method comprising:
Dependencies are inferred from the claim text.