Devices and methods for preventing errors and detecting faults within a memory device

A data processing system

• a memory configured to receive memory access requests, each memory access request having a corresponding access address and having a corresponding parity bit for an address value of the corresponding access address, wherein the corresponding access address is received over a plurality of address lines and the parity bit is received over a parity line, the memory having:
• a memory array having a plurality of memory cells arranged in rows, each row having a corresponding word line of a plurality of word lines;
• a row decoder coupled to the plurality of address lines, the parity line, and the plurality of word lines, and configured to selectively activate a selected word line of the plurality of word lines based on the corresponding access address and the corresponding parity bit of a received memory access request;
• and
• parity error circuitry coupled to the plurality of address lines and the parity line, and configured to provide a parity error indicator which indicates if the address value of the corresponding access address has a parity error or not, wherein, for each row, the parity error circuitry comprises:
• a corresponding pull-down transistor;
• and
• corresponding parity error logic coupled to the plurality of address lines and the parity line and having an output coupled to a control electrode of the corresponding pull-down transistor, wherein the corresponding parity error logic is configured to activate the corresponding pull-down transistor when a parity error exists for a memory access to the row, and not activate the pull-down transistor when parity is correct for the memory access to the row.

A data processing system

• a memory configured to receive memory access requests, each memory access request having a corresponding access address and having a corresponding parity bit for an address value of the corresponding access address, wherein the corresponding access address is received over a plurality of address lines and the parity bit is received over a parity line, the memory having:
• a memory array having a plurality of memory cells arranged in rows, each row having a corresponding word line of a plurality of word lines;
• and
• a row decoder coupled to the plurality of address lines, the parity line, and the plurality of word lines, and configured to selectively activate a selected word line of the plurality of word lines based on the corresponding access address and the corresponding parity bit of a received memory access request,
• wherein, for each row, the row decoder comprises:
• corresponding decoder logic coupled to the plurality of address lines and the parity line and configured to provide a select indicator, wherein the select indicator is asserted when an access address addresses the row and a parity bit corresponding to the access address indicates correct parity for an address value of the access address;
• and
• a corresponding first latch coupled to the corresponding decoder logic to latch the select indicator, wherein the corresponding word line of the row is activated when at least the latched select indicator is asserted.

A data processing system comprising:

• a system interconnect;
• an initiator configured to provide memory access requests to the memory via the system interconnect;
• a memory configured to receive the memory access requests, each memory access request having a corresponding access address and having a corresponding parity bit for an address value of the corresponding access address, wherein the corresponding access address is received over a plurality of address lines and the parity bit is received over a parity line, the memory having:
• a memory array having a plurality of memory cells arranged in rows, each row having a corresponding word line of a plurality of word lines;
• a row decoder coupled to the plurality of address lines, the parity line, and the plurality of word lines, and configured to selectively activate a selected word line of the plurality of word lines based on the corresponding access address and the corresponding parity bit of a received memory access request.

A data processing system comprising:

• a memory configured to receive memory access requests, each memory access request having a corresponding access address and having a corresponding parity bit for an address value of the corresponding access address, wherein the corresponding access address is received over a plurality of address lines and the parity bit is received over a parity line, the memory having:
• a memory array having a plurality of memory cells arranged in rows, each row having a corresponding word line of a plurality of word lines;
• and
• a row decoder coupled to the plurality of address lines, the parity line, and the plurality of word lines, and configured to selectively activate a selected word line of the plurality of word lines based on the corresponding access address and the corresponding parity bit of a received memory access request,
• wherein, for each row, the row decoder includes corresponding parity error logic configured to determine whether or not a parity error exists based on the values on the plurality of address lines and the parity line provided for a memory access to the row.