Programming codewords for error correction operations to memory
AssigneeMicron Technology, Inc.
InventorMarco Sforzin
Life of this patent
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Abstract
The present disclosure includes apparatuses, methods, and systems for programming codewords for error correction operations to memory. An embodiment includes a memory having a plurality of groups of memory cells, wherein each respective one of the plurality of groups includes a plurality of sub-groups of memory cells, and circuitry configured to program a portion of a codeword for an error correction operation to one of the plurality of groups of memory cells by determining an address in that group of memory cells by performing an XOR operation on an address of one of the plurality of sub-groups of that group of memory cells, and programming the portion of the codeword to the determined address.
Claims16
An apparatus, comprising:
- a memory having a plurality of groups of memory cells, wherein each respective one of the plurality of groups includes a plurality of sub-groups of memory cells;
- and
- circuitry configured to program a portion of a codeword for an error correction operation to one of the plurality of groups of memory cells by:
- determining an address in that group of memory cells by performing an XOR operation on any portion of an address of one of the plurality of sub-groups of that group of memory cells;
- and
- programming the portion of the codeword to the determined address.
A method of operating memory, comprising:
- programming a portion of a codeword for an error correction operation to one of a plurality of groups of memory cells of the memory by:
- determining an address in that group of memory cells by performing an XOR operation on any portion of an address of one of a plurality of sub-groups of memory cells of that group of memory cells;
- and
- programming the portion of the codeword to the determined address.
An apparatus, comprising:
- a memory having a plurality of groups of memory cells, wherein each respective one of the plurality of groups includes a plurality of sub-groups of memory cells;
- and
- circuitry configured to program a different portion of a codeword for an error correction operation to each respective one of the plurality of groups of memory cells by:
- determining an address in each respective one of the plurality of groups of memory cells by performing an XOR operation on an address of a sub-group of that respective group of memory cells;
- and
- programming a different portion of the codeword to each respective determined address.
Dependencies are inferred from the claim text.