String based erase inhibit
AssigneeSanDisk Technologies LLC
InventorHideto Tomiie
Life of this patent
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AssigneeSanDisk Technologies LLC
InventorHideto Tomiie
Estimating the term…
A non-volatile memory device, described herein, comprises: a plurality of memory strings and at least one control circuit in communication with the non-volatile memory cell array. The at least one control circuit is configured to perform, for the plurality of memory strings, one erase-verify iteration in an erase operation including determining whether at least one memory string of the plurality of memory strings passes an erase-verify test. The at least one control circuit is configured to, if the at least one memory string passes the erase-verify test, inhibit the at least one memory string for erase including ramping up, to an erase voltage, of a voltage applied to a gate of a SGD transistor of the at least one memory string and to perform a next erase-verify iteration in the erase operation for remaining memory strings of the plurality of memory strings other than the at least one memory string.
A non-volatile memory device, comprising:
A method of operating a memory apparatus comprising a plurality of memory strings, each memory string of the plurality of memory strings comprising a plurality of memory cells arranged between a select gate drain (SGD) transistor at a drain-side end of a memory string and a select gate source (SGS) transistor at a source-side end of the memory string, the method comprising the steps of:
An apparatus comprising:
Dependencies are inferred from the claim text.