US 11,769,559 B2 · Methods of reducing program disturb by array source coupling in 3D NAND memory devices

Abstract

The present disclosure provides a three-dimensional NAND memory device, comprising a first NAND string including a first channel corresponding to a first cell to be inhibited to program, and a controller configured to control a word line driver and a bit line driver to do the following operations: prior to applying a program voltage to a selected word line, charging a first bit line electrically coupling with the first channel to a first voltage level for charging the first channel to the first voltage level, charging an array common source electrically coupling with the first bit line for further charging the first channel to a second voltage level higher than the first voltage level, and cutting off the electrical coupling between the first bit line and the first channel for preparing to apply the program voltage to the selected word line.

Claims20

Dependent claims

A three-dimensional (3D) NAND memory device, comprising:

a first NAND string including a first channel corresponding to a first cell to be inhibited to program;
a word line driver;
a bit line driver;
and
a controller configured to control the word line driver and the bit line driver to:
(a) prior to applying a program voltage to a selected word line, charge a first bit line electrically coupling with the first channel to a first voltage level for charging the first channel to the first voltage level,
(b) charge an array common source electrically coupling with the first bit line for further charging the first channel to a second voltage level higher than the first voltage level, and
(c) cut off the electrical coupling between the first bit line and the first channel for preparing to apply the program voltage to the selected word line.

5 more elements

A three-dimensional (3D) NAND memory device, comprising:

a first NAND string including a first channel corresponding to a first cell to be inhibited to program;
a word line driver;
a bit line driver;
and
a controller configured to control the word line driver and the bit line driver to:
(a) prior to applying a program voltage to a selected word line, charge an array common source electrically coupling with the first channel to a first voltage level for charging the first channel to the first voltage level, wherein the first channel corresponds to a first cell, to be inhibited to program, in the first NAND string,
(b) charge a first bit line electrically coupling with the array common source for further charging the first channel to a second voltage level higher than the first voltage level, and
(c) cut off the electrical coupling between the array common source and the first channel for preparing to apply the program voltage to the selected word line.

5 more elements

Dependencies are inferred from the claim text.

Methods of reducing program disturb by array source coupling in 3D NAND memory devices

Life of this patent

Methods of reducing program disturb by array source coupling in 3D NAND memory devices

Life of this patent

Abstract

Claims20