Semiconductor memory device

A semiconductor memory device, comprising:

• a substrate;
• a memory pillar extending in a first direction from the substrate;
• a first conductive layer provided above the substrate, the first conductive layer being provided separately from the substrate in the first direction, the first conductive layer being provided in parallel with a substrate surface of the substrate, and the first conductive layer facing the memory pillar;
• a second conductive layer provided above the substrate, the second conductive layer being provided to be adjacent to the first conductive layer with the memory pillar interposed between the first conductive layer and the second conductive layer in a second direction crossing the first direction, the second conductive layer being provided in parallel with the substrate surface, and the second conductive layer facing the memory pillar;
• a third conductive layer provided between the substrate and the first conductive layer, the third conductive layer being provided in parallel with the substrate surface, and the third conductive layer facing the memory pillar;
• a fourth conductive layer provided between the substrate and the second conductive layer, the fourth conductive layer being provided to be adjacent to the third conductive layer with the memory pillar interposed between the third conductive layer and the fourth conductive layer in the second direction, the fourth conductive layer being provided in parallel with the substrate surface, and the fourth conductive layer facing the memory pillar;
• a fifth conductive layer provided above the first conductive layer, the fifth conductive layer being in parallel with the substrate surface, and the fifth conductive layer facing the memory pillar;
• a sixth conductive layer provided above the second conductive layer, the sixth conductive layer being provided to be adjacent to the fifth conductive layer with the memory pillar interposed between the fifth conductive layer and the sixth conductive layer in the second direction, the sixth conductive layer being provided in parallel with the substrate surface, and the sixth conductive layer facing the memory pillar;
• a seventh conductive layer provided between the substrate and the third conductive layer, the seventh conductive layer being provided in parallel with the substrate surface, and the seventh conductive layer facing the memory pillar;
• an eighth conductive layer provided between the substrate and the fourth conductive layer, the eighth conductive layer being provided to be adjacent to the seventh conductive layer with the memory pillar interposed between the seventh conductive layer and the eighth conductive layer in the second direction, the eighth conductive layer being provided in parallel with the substrate surface, and the eighth conductive layer facing the memory pillar;
• a ninth conductive layer provided above the fifth conductive layer, the ninth conductive layer being provided in parallel with the substrate surface, and the ninth conductive layer facing the memory pillar;
• a tenth conductive layer provided above the sixth conductive layer, the tenth conductive layer being provided to be adjacent to the ninth conductive layer with the memory pillar interposed between the ninth conductive layer and the tenth conductive layer in the second direction, the tenth conductive layer being provided in parallel with the substrate surface, and the tenth conductive layer facing the memory pillar;
• a first memory cell formed between the first conductive layer and the memory pillar;
• a second memory cell formed between the second conductive layer and the memory pillar;
• a third memory cell formed between the third conductive layer and the memory pillar;
• a fourth memory cell formed between the fourth conductive layer and the memory pillar;
• a fifth memory cell formed between the fifth conductive layer and the memory pillar;
• a sixth memory cell formed between the sixth conductive layer and the memory pillar;
• a seventh memory cell formed between the seventh conductive layer and the memory pillar;
• an eighth memory cell formed between the eighth conductive layer and the memory pillar;
• a ninth memory cell formed between the ninth conductive layer and the memory pillar;
• a tenth memory cell formed between the tenth conductive layer and the memory pillar;
• and
• a control circuit, when reading data from the first memory cell, the control circuit applying a first voltage to the first conductive layer, the second conductive layer, the fourth conductive layer, the sixth conductive layer, the seventh conductive layer, the eighth conductive layer, the ninth conductive layer, and the tenth conductive layer and applying a second voltage higher than the first voltage to the third conductive layer and the fifth conductive layer, then applying a third voltage lower than the first voltage to the first conductive layer, applying a fourth voltage lower than the first voltage to the eighth conductive layer and the tenth conductive layer, and applying a fifth voltage lower than the first voltage to the second conductive layer, the fourth conductive layer, and the sixth conductive layer, and then applying a sixth voltage higher than the third voltage and lower than the first voltage to the first conductive layer, applying a seventh voltage different from the fourth voltage and lower than the first voltage to the eighth conductive layer and the tenth conductive layer, and applying an eighth voltage lower than the fifth voltage to the second conductive layer, the fourth conductive layer, and the sixth conductive layer.