Ramp-based biasing and adjusting of access line voltage in a memory device

#This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present techniques, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light and not as admissions of prior art.

#Generally, a computing system includes processing circuitry, such as one or more processors or other suitable components, and memory devices, such as chips or integrated circuits. One or more memory devices may be used on a memory module, such as a dual in-line memory module (DIMM), to store data accessible to the processing circuitry. For example, based on a user input to the computing system, the processing circuitry may request that a memory module retrieve data corresponding to the user input from its memory devices. In some instances, the retrieved data may include firmware, or instructions executable by the processing circuitry to perform an operation and/or may include data to be used as an input for the operation. In addition, in some cases, data output from the operation may be stored in memory, such as to enable subsequent retrieval of the data from the memory.

#Some memory devices include memory cells that may be accessed by turning on a transistor that couples the memory cell (e.g., a capacitor) with a wordline or a bitline. In contrast, threshold-type memory devices include memory devices that are accessed by providing a voltage across a memory cell, where the data value is stored based on the threshold voltage of the memory cell. For example, the data value may be based on whether the threshold voltage of the memory cell is exceeded and, in response to the voltage provided across the memory cell, the memory cell conducts current. The data value stored may be changed, such as by applying a voltage sufficient to change the threshold voltage of the memory cell. One example of a threshold-type memory cell may be a cross-point memory cell.

#Various aspects of this disclosure may better be understood upon reading the following detailed description and upon reference to the drawings in which:

#FIG. 1 is a simplified block diagram illustrating certain features of a memory device including a memory array of memory cells, according to an embodiment of the present disclosure;

#FIG. 2 is a side-view of a diagram illustrating the portion of the memory array of FIG. 1, according to an embodiment of the present disclosure;

#One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

#Memories generally include an array of memory cells, where each memory cell is coupled between at least two access lines. For example, a memory cell may be coupled to access lines, such as a bitline and a wordline. Each access line may be coupled to a large number of memory cells. To select a memory cell, one or more drivers may provide selection signals (e.g., a voltage and/or a current) on the access lines to access storage capacities of the memory cell. By applying voltages and/or currents to the respective access lines, the memory cell may be accessed, such as to write data to the memory cell and/or read data from the memory cell.

#In some memories, memory cells of the array may be organized into decks of memory cells. A deck of memory cells may be a single plane of memory cells disposed between a layer of wordlines and a layer of bitlines. The array may be a stack of decks that includes any number of decks of memory cells (e.g., 0 decks, 1 deck, 2 decks, 4 decks, any number of decks) as different layers of the array.