Multi-level self-selecting memory device

A memory device, comprising:

• a memory array comprising self-selecting memory cells;
• and
• a controller coupled with the memory array, the controller operable to cause the memory device to:
• determine a desired threshold voltage of a self-selecting memory (SSM) cell that comprises a chalcogenide alloy, a first side of the chalcogenide alloy interfacing with a first electrode and a second side of the chalcogenide alloy interfacing with a second electrode, and the desired threshold voltage corresponding to a desired logic state of the SMM cell representing more than one bit of data;
• determine a polarity and an amplitude of a programming pulse based at least in part on the desired threshold voltage of the SMM cell;
• set the polarity of the programming pulse based at least in part on a present state of the SSM cell and the desired logic state of the SSM cell;
• and
• alter a spatial distribution of at least one part of the chalcogenide alloy by applying the programming pulse to the SMM cell based at least in part on determining the polarity and the amplitude of the programming pulse, wherein the desired threshold voltage of the SSM cell is based at least in part on the spatial distribution of the at least one part of the chalcogenide alloy.