Memory device comprising an electrically floating body transistor

A semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each of said semiconductor memory cells comprises:

• a first bipolar device having a first floating base region, a first collector, and a first emitter;
• a second bipolar device having a second floating base region, a second collector, and a second emitter;
• a third bipolar device having a third floating base region, a third collector, and a third emitter;
• a fourth bipolar device having a fourth floating base region, a fourth collector, and a fourth emitter;
• a fifth bipolar device having a fifth floating base region, a fifth collector, and a fifth emitter;
• and
• a gate region positioned in between said first collector and said first emitter, said gate region positioned in between said second collector and said second emitter, said gate region being positioned in between said third collector and said third emitter, said gate region being positioned in between said fourth collector and said fourth emitter, and said gate region being positioned in between said fifth collector and said fifth emitter;
• wherein said first floating base region, said second floating base region, said third floating base region, said fourth floating base region, and said fifth floating base region are common and are configured to be charged to a level indicative of a state of said semiconductor memory cell;
• wherein said first collector and said second collector are common;
• wherein said fourth collector and said fifth collector are common;
• wherein said state of said semiconductor memory cell is maintained through a bias applied through said first and second collectors or through a bias applied through said fourth and fifth collectors;
• wherein said first and second collectors are commonly connected to at least two of said semiconductor memory cells;
• wherein said fourth and fifth collectors are commonly connected to at least two of said semiconductor memory cells;
• wherein when a first semiconductor memory cell of said at least two of said semiconductor memory cells is in a first state and a second semiconductor memory cell of said at least two of said semiconductor memory cells is in a second state, application of said bias applied through said first and second collectors or through said bias applied through said fourth and fifth collectors maintains said first semiconductor memory cell in said first state and said second semiconductor memory cell in said second state.