Memory device transmitting and receiving data at high speed and low power
AssigneeSamsung Electronics Co., Ltd.
InventorsByongmo Moon, Jihye Kim, Je Min Ryu, Beomyong Kil, Sungoh Ahn
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Abstract
A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.
Claims19
A method for using a high bandwidth memory controller, the method comprising:
- providing a clock signal having a first clock frequency;
- providing a write strobe signal having a second clock frequency;
- providing a write command/address signal based on the clock signal;
- providing a write data signal based on the write strobe signal;
- generating, by a phase locked loop, a first internal clock signal;
- generating, by a phase controller, a second internal clock signal based on the first internal clock signal;
- dividing, by an internal clock divider, the first internal clock signal to generate a first divided internal clock signal and a second divided internal clock signal;
- generating, by a first transmitter, the write data signal including write data based on the second internal clock signal;
- generating, by a second transmitter, the first internal clock signal as the write strobe signal;
- generating, by a third transmitter, the first divided internal clock signal as the clock signal;
- and
- generating, by a fourth transmitter, the write command/address signal based on the second divided internal clock signal,
- wherein the first clock frequency is half of the second clock frequency, and
- wherein the write strobe signal has two cycles of pre-amble before the write data signal and the write strobe signal has two cycles of post-amble after the write data signal.
A method for using a high bandwidth memory controller, the method comprising:
- providing a clock signal having a first clock frequency;
- providing a write strobe signal having a second clock frequency;
- providing a read command/address signal based on the clock signal;
- receiving a read data signal based on a read strobe signal generated from the write strobe signal;
- and
- wherein the first clock frequency is half of the second clock frequency, and
- wherein the read strobe signal has a plurality of pre-amble cycles before the read data signal and the read strobe signal has a plurality of post-amble cycles after the read data signal.
A memory controller comprising:
- a phase locked loop configured to generate a first internal clock signal;
- a phase controller configured to generate a second internal clock signal based on the first internal clock signal;
- an internal clock divider configured to divide the first internal clock signal to generate a first divided internal clock signal and a second divided internal clock signal;
- a first transmitter configured to transmit a write data signal including write data based on the second internal clock signal;
- a second transmitter configured to transmit the first internal clock signal as a write strobe signal;
- a third transmitter configured to transmit the first divided internal clock signal as a clock signal;
- and
- a fourth transmitter configured to transmit the write command/address signal based on the second divided internal clock signal.
Dependencies are inferred from the claim text.