Integrated circuit with asymmetric arrangements of memory arrays

A method, comprising:

• generating at least one control signal by a decoder circuit;
• controlling, based on the at least one control signal, a first pair of complementary data lines coupled to a first array of memory cells;
• and
• controlling, based on the at least one control signal, a second pair of complementary data lines coupled to a second array of memory cells,
• wherein a plurality of first word lines is arranged in a first segment of a memory bank, and coupled to the first array of memory cells,
• a plurality of second word lines is arranged in a second segment of the memory bank, that is disposed between the first segment and a sense amplifier, and the plurality of second word lines being coupled to the second array of memory cells,
• lengths of the first pair of complementary data lines are shorter than lengths of the second pair of complementary data lines,
• the plurality of first word lines and the plurality of second word lines are arranged according to a predetermined ratio of a number of the plurality of first word lines to a number of the plurality of second word lines, and
• the predetermined ratio is less than 1.

A method, comprising:

• generating at least one control signal by a decoder circuit;
• controlling a memory bank based on the at least one control signal;
• and
• operating, by an access circuit, a read or write operation of the memory bank through a pair of conducting lines, and a pair of complementary data lines,
• wherein the memory bank comprises a first segment, a second segment and a strap cell,
• the first segment comprises a first array of memory cells,
• the second segment comprises a second array of memory cells,
• the strap cell is arranged between the first segment and the second segment,
• the first segment and the second segment are asymmetric with respect to the strap cell, and
• the pair of conducting lines are coupled to the first array of memory cells, and the pair of complementary data lines are coupled to the second array of memory cells.