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US 11,769,537 B2Granted
Memory device and memory system including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsByunghoon Jeong, Kyungtae Kang, Jangwoo Lee, Jeongdon Ihm
Life of this patent
Estimating the term…
Abstract
A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.
Claims20
A memory device, comprising:
- a memory cell array configured to store data;
- and
- a data output circuit configured to transmit a data signal to an external device, wherein the data output circuit includes:
- a latch register configured to store the data read from the memory cell array;
- a status register configured to store status data;
- and
- a multiplexer configured to select first output data of the status register during a latency period and second output data of the latch register during a period subsequent to the latency period.
4 more elements
A memory device, including:
- a memory cell array configured to store data;
- and
- a data output circuit configured to selectively transmit one of status data and the data stored in the memory cell array to an external device as a data signal based on whether a transmission period is a latency period, wherein the data output circuit includes,
- a latency counter configured to count a numbers of cycles of an initial data strobe signal in response to receipt of a read enable signal to identify whether the transmission period is the latency period.
1 more element
Dependencies are inferred from the claim text.