Shift register unit set, gate driving circuit and display apparatus

A shift register, comprising:

• a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a banking output control signal;
• a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal;
• an output sub-circuit, configured to output a composite output signal via an output terminal under control of a first node, wherein the composite output signal includes a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other,
• wherein the first input sub-circuit comprises:
• a storing sub-circuit, having a terminal is connected to a blanking pull-up control node, configured to store a blanking pull-up control signal;
• and
• an isolating sub-circuit, configured to input a blanking output control signal to the first node according to the blanking pull-up control signal in a blanking period of time of a frame, said isolating sub-circuit comprising an isolating transistor,
• said shift register further comprising:
• a first electric leakage prevention sub-circuit configured to input an operating potential to a first electrode of the isolation transistor under the control of the blanking pull-up control node;
• and a second electric leakage prevention sub-circuit configured to input the operating potential to a second electrode of the isolation transistor under the control of the first node,
• the first electric leakage prevention sub-circuit comprises a first electric leakage prevention transistor and a second electric leakage prevention transistor, a first electrode of the first electric leakage prevention transistor is connected to the blanking pull-up control node, a second electrode of the first electric leakage prevention transistor is connected to a first electrode of the isolating transistor, and a control electrode of the first electric leakage prevention transistor is connected to a control electrode of the isolating transistor, a first electrode of the second electric leakage prevention transistor is connected to a electric leakage prevention signal input terminal, a second electrode of the second electric leakage prevention transistor is connected to the second electrode of the first electric leakage prevention transistor, and a control electrode of the second electric leakage prevention transistor is connected to the blanking pull-up control node,
• the second electric leakage prevention sub-circuit comprises a third electric leakage prevention transistor and a fourth electric leakage prevention transistor, a first electrode of the third electric leakage prevention transistor is connected to the first node, a second electrode of the third electric leakage prevention transistor is connected to the second electrode of the isolating transistor, and a control electrode of the third electric leakage prevention transistor is connected to the control electrode of the isolating transistor, a first electrode of the fourth electric leakage prevention transistor is connected to the electric leakage prevention signal input signal, a second electrode of the fourth electric leakage prevention transistor is connected to the second electrode of the third electric leakage prevention transistor, and a control electrode of the fourth electric leakage prevention transistor is connected to the first node.