Shift register unit set, gate driving circuit and display apparatus

A gate driving circuit, comprising a shift register unit set, comprising:

• cascaded n shift register units, and an i-th stage of shift register unit in the shift register unit set comprises:
• a second input sub-circuit configured to receive a second input signal from a second input terminal, and input a display pull-up signal to a first pull-up node according to the second input signal in a display period of time of a frame;
• and
• a first input sub-circuit configured to receive a first input signal from a first input terminal, and input a blanking pull-up signal to the first pull-up node according to the first input signal in a blanking period of time of a frame, wherein the first input sub-circuit comprises:
• a charging sub-circuit, configured to input the first input signal to a blanking pull-up control node;
• a storing sub-circuit, having a terminal is connected to the blanking pull-up control node, configured to store a blanking pull-up control signal;
• an isolating sub-circuit, configured to input the blanking pull-up signal to the first pull-up node according to the first input signal in the blanking period of time of a frame, the isolating sub-circuit comprising an isolating transistor;
• an output sub-circuit configured to output a composite output signal via an output terminal under the control of the first pull-up node;
• a first electric leakage prevention sub-circuit configured to input an operation potential to the isolating sub-circuit under the control of the blanking pull-up control node;
• and
• a second electric leakage prevention sub-circuit configured to input the operation potential to a second electrode of the isolating transistor under the control of the first pull-up node,
• wherein there is an overlap among n composite output signals output by the n shift register units, where n and i are positive integers, and 1≤i≤n.