Display panel and display device having emission control driver

A display panel comprising:

• a display area configured to display an image through sub pixels;
• a bezel area surrounding or being adjacent to the display area;
• a first scan driver embedded in the bezel area and configured to supply a plurality of first scan signals to a plurality of first gate lines connected to the sub pixels;
• a second scan driver embedded in the bezel area and configured to supply a plurality of second scan signals to a plurality of second gate lines connected to the sub pixels;
• and
• an emission control driver embedded in the bezel area and configured to supply a plurality of emission control signals to a plurality of third gate lines connected to the sub pixels,
• wherein the emission control driver includes a plurality of emission control stages configured to supply the plurality emission control signals, respectively, and
• wherein each of the plurality of emission control stages includes:
• an output buffer including:
• a first pull-up transistor configured to output a first high potential power supply voltage to an output line by a first control node,
• a second pull-up transistor configured to output a second high potential power supply voltage to a carry output line by the first control node,
• a first pull-down transistor configured to output a first low potential power supply voltage to the output line by a second control node, and
• a second pull-down transistor configured to output the first low potential power supply voltage to the carry output line by the second control node;
• a charge/discharge part configured to charge and discharge the first control node by using a charge/discharge signal in response to a clock signal;
• an inverter configured to charge and discharge the second control node to be opposite to the first control node;
• a first back bias circuit configured to apply a first back bias voltage to a light shielding layer of at least one transistor of the output buffer through a first back bias node capacitance-coupled to the first control node;
• and
• a second back bias circuit configured to apply a second back bias voltage to a light shielding layer of at least one transistor of the inverter through a second back bias node capacitance-coupled to the second control node, and
• wherein the first back bias circuit includes:
• the first back bias node connected to the light shielding layer of at least one of the first and second pull-up transistors of the output buffer;
• a first capacitor connected between the first control node and the first back bias node;
• and
• a first back bias transistor configured to initialize the first back bias node to a second low potential power supply voltage, which is lower than the first low potential power voltage, during a vertical blank period of each frame by a stabilization signal, and floating the first back bias node during an active period of each frame.