Shift-register unit circuit, gate-driving circuit, display apparatus, and driving method

A shift-register unit circuit comprising:

• a first input sub-circuit configured to have a display-input terminal to receive a display-input signal, and to provide a display output-control signal to a first node based on the display-input signal;
• a second input sub-circuit configured to have a blank-input terminal to receive a blank-input signal for charging a blank-control node, and to provide a blank output-control signal to the first node based on the blank-input signal;
• an output sub-circuit configured to have an output terminal to output a hybrid output signal under control of the first node, the hybrid output signal being a display-output signal under control of the display output-control signal and a blank-output signal under control of the blank output-control signal;
• a first control sub-circuit, configured to control a voltage level a second node under control of the first node;
• and
• a second control sub-circuit configured to pull down voltage levels of the first node and the output terminal to turn-off voltage levels under control of the second node;
• wherein the second input sub-circuit is configured to provide the blank output-control signal to the first node based on a blank-control signal;
• the first control sub-circuit comprises a first control transistor and a second control transistor, the first control transistor having a first terminal and a control terminal commonly connected to a first pull-down control-signal line, and a second terminal connected to the second node;
• the second control transistor having a first terminal connected to the second node, a control terminal connected to the first node, and a second terminal connected to a first signal line providing a turn-off voltage level;
• and
• the second control sub-circuit comprises a first pull-down transistor and a second pull-down transistor, the first pull-down transistor having a first terminal connected to the first node, a control terminal connected to the second node, and a second terminal connected to the first signal line providing the turn-off voltage level;
• the second pull-down transistor having a first terminal connected to the output terminal, a control terminal connected to the second node, and a second terminal connected to the first signal line providing the turn-off voltage level.