Superconducting circuit structure, superconducting quantum chip and superconducting quantum computer

A superconducting quantum chip, wherein at least a superconducting circuit structure is formed on the superconducting quantum chip, wherein the superconducting circuit structure comprises:

• at least three computational qubits;
• a bus qubit connected to the at least three computational qubits, wherein couplings between two of the at least three computational qubits connected by the bus qubit are equivalent;
• at least three coupler qubits, wherein a number of coupler qubits is same as a number of computational qubits, wherein each of the at least three coupler qubits is disposed between a respective computational qubit and the bus qubit, to connect the respective computational qubits to the bus qubit, and the each of the at least three coupler qubits is configured to regulate coupling strength between the respective computational qubit and the bus qubit;
• and
• a first connector, a second connector, and a third connector,
• wherein a first end of the bus qubit is connected to a first end of each of the at least three computational qubits through the first connector, a second end of the bus qubit is connected to a first end of each of the at least three coupler qubits through the second connector, and a second end of each of the at least three computational qubits is connected to a second end of a respective coupler qubit through the third connector.

A superconducting quantum computer, provided at least with a superconducting quantum chip and a control and reading device connected to the superconducting quantum chip, wherein a superconducting circuit structure is formed on the superconducting quantum chip and the superconducting circuit structure comprises:

• at least three computational qubits;
• a bus qubit connected to the at least three computational qubits, wherein couplings between two of the at least three computational qubits connected by the bus qubit are equivalent;
• at least three coupler qubits, wherein a number of coupler qubits is same as a number of computational qubits, wherein each of the at least three coupler qubits is disposed between a respective computational qubit and the bus qubit, to connect the respective computational qubits to the bus qubit, and the each of the at least three coupler qubits is configured to regulate coupling strength between the respective computational qubit and the bus qubit;
• a first connector, a second connector, and a third connector, and
• wherein a first end of the bus qubit is connected to a first end of each of the at least three computational qubits through the first connector, a second end of the bus qubit is connected to a first end of each of the at least three coupler qubits through the second connector, and a second end of each of the at least three computational qubits is connected to a second end of a respective coupler qubit through the third connector.