Scalable multi-die deep learning system

A semiconductor chip comprising:

• a plurality of processing elements;
• a global memory buffer;
• at least one controller to distribute weights and activations for layers of a neural network spatially across the processing elements by input output channel dimensions and temporally by input height and width;
• the at least one controller to utilize the global memory buffer as a second-level buffer for the activations;
• at least one multiply-accumulate unit comprising:
• a weight collector disposed in a data flow between (i) a weight buffer configured to receive and store the weights from the controller and (ii) the multiply-accumulate unit;
• and
• an accumulation collector disposed in the data flow between the multiply-accumulate unit and an accumulation memory buffer.

A semiconductor neural network processor, comprising:

• a plurality of chips, each chip comprising a plurality of processing elements;
• each of the processing elements comprising:
• a plurality of multiply-accumulate units;
• an accumulation memory buffer;
• a weight buffer;
• each multiply-accumulate unit comprising:
• a weight collector of configurable depth disposed in a data flow between the weight buffer and each multiply-accumulate unit;
• and
• an accumulation collector of configurable depth disposed in a data flow between each multiply-accumulate unit and the accumulation memory buffer.