Pin access hybrid cell height design
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKam-Tou Sio, Jiann-Tyng Tzeng
Life of this patent
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Abstract
A method of generating a layout diagram for an integrated circuit. The method includes arranging a plurality of cells in the layout diagram. The method further includes placing a plurality of cell pins over a plurality of selected via placement points in a first cell of the plurality of cells, wherein at least one cell pin of the plurality of cell pins extends along a routing track of a plurality of routing tracks across a boundary of the first cell and into a second cell of the plurality of cells abutting the first cell.
Claims20
A method of generating a layout diagram for an integrated circuit, the method comprising:
- arranging a plurality of cells in the layout diagram;
- and
- placing a plurality of cell pins over a plurality of selected via placement points in a first cell of the plurality of cells, wherein at least one cell pin of the plurality of cell pins extends along a routing track of a plurality of routing tracks across a boundary of the first cell and into a second cell of the plurality of cells abutting the first cell.
A non-transitory computer readable medium having instructions stored thereon, which when executed by a processor, cause the processor to:
- arrange a plurality of cells in a layout diagram;
- and
- place a plurality of cell pins over a plurality of selected via placement points in a first cell of the plurality of cells, wherein at least one cell pin of the plurality of cell pins extends along a routing track of a plurality of routing tracks across a boundary of the first cell and into a second cell of the plurality of cells abutting the first cell.
A method of generating a layout diagram for an integrated circuit, the method comprising:
- arranging a plurality of cells in the layout diagram, wherein a first cell of the plurality of cells forms an interface with a second cell of the plurality of cells, and a plurality of routing tracks extend across the interface;
- and
- placing a plurality of cell pins over a plurality of selected via placement points in the first cell, wherein a first cell pin of the plurality of cell pins extends along a first routing track of the plurality of routing tracks, and the first cell pin extends across the interface.
Dependencies are inferred from the claim text.