Standard unit for system on chip design, and data processing unit, operation chip and computing apparatus using same

A standard unit for a system on chip design, comprising a plurality of semiconductor devices and configured to implement a basic logic function, wherein the plurality of semiconductor devices comprise:

• a first transistor of a first threshold type;
• and
• a second transistor of a second threshold type, wherein when the second transistor has a same threshold type as that of the first transistor, a second path speed of the second transistor is lower than a first path speed of the first transistor;
• wherein a threshold of the first threshold type is selected to be higher than that of the second threshold type to balance the first path speed of the first transistor and the second path speed of the second transistor, so that rising delay time and falling delay time of the standard unit are balanced.