Tamper detection device, system, and method

A tamper detection device for detecting tampering with respect to a packaging, wherein the device comprises:

• a first electrode comprising a first patterned structure;
• a second electrode comprising a second patterned structure;
• wherein the first electrode and the second electrode are arranged so that the first patterned structure and the second patterned structure are at least partially opposite to each other,
• wherein, in a first arrangement state of the first patterned structure and the second patterned structure with respect to each other, a first capacitance is measurable,
• wherein, in a second arrangement state of the first patterned structure and the second patterned structure with respect to each other, a second capacitance is measurable,
• wherein the first capacitance is different from the second capacitance, and wherein the first arrangement state is different from the second arrangement state;
• and
• a detection unit, wherein the detection unit is configured to:
• measure the capacitance between the first electrode and the second electrode,
• obtain, based on the measured capacitance, an information indicative of the arrangement state, and
• evaluate, based on the information indicative of the arrangement state, if a tampering with respect to the packaging is detected, wherein tampering is not detected when the first patterned structure and the second patterned structure are in the first arrangement state wherein a high level of correlation between the first patterned structure and the second patterned structure is obtained, and wherein tampering is detected when the first patterned structure and the second patterned structure are in the second arrangement state wherein a low level of correlation between the first patterned structure and the second patterned structure is obtained, and wherein the measured capacitance is at its maximum or at its minimum in the first arrangement state, and wherein the measured capacitance is not at its maximum or at its minimum in the second arrangement state.