Security plugin for a system-on-a-chip platform
AssigneeIntel Corporation
InventorsManoj R. Sastry, Alpa Narendra Trivedi, Men Long
Life of this patent
Estimating the term…
Abstract
Systems and techniques for a System-on-a-Chip (SoC) security plugin are described herein. A component message may be received at an interconnect endpoint from an SoC component. The interconnect endpoint may pass the component message to a security component via a security interlink. The security component may secure the component message, using a cryptographic engine, to create a secured message. The secured message is delivered back to the interconnect endpoint via the security interlink and transmitted across the interconnect by the interconnect endpoint.
Claims18
A system for apparatus of a system-on-a-chip platform, the system comprising:
- a security block including:
- a cryptographic circuit including:
- a cryptographic engine selected from a plurality of cryptographic engines;
- and
- a standard interface that is generic to the plurality of cryptographic engines, the standard interface being bi-directional between the cryptographic engine and a requester;
- a cryptographic controller to manage a cryptographic key used by the cryptographic engine;
- and
- a cryptographic state manager to manage cryptographic session states between an initiator component and a destination component;
- and
- a system-on-a-chip interconnect endpoint coupled to an interconnect of the system-on-a-chip, the interconnect coupled to a plurality of system-on-a-chip interconnect endpoints, the plurality of system-on-a-chip interconnect endpoints coupled to components of the system-on-a-chip, the system-on-a-chip interconnect interface including:
- a component facing transceiver to send or receive component messages to components;
- an interconnect packager to convert a component message received from a component to an interconnect message and to convert the interconnect message received from another interconnect endpoint into a component message;
- and
- a security interconnect conforming to the standard interface of the cryptographic circuit of the security block, the security interconnect interposed between communications of the component facing transceiver and the interconnect packager, wherein a component message received by the component facing transceiver is passed to the security circuit via the standard interface to create an encrypted message which is returned via the standard interface to be packaged by the interconnect packager prior to transmission on the interconnect.
A system for using an apparatus for a system-on-a-chip, the system comprising:
- means for receiving a component message at a bus endpoint from a system-on-a-chip component;
- means for passing, by the bus endpoint, the component message to a security component via a security interconnect;
- means for receiving the component message by the security component via the security interconnect;
- means for encrypting the component message using a cryptographic engine, the cryptographic engine being one of a plurality of cryptographic engines, the security interconnect being the same for all of the plurality of cryptographic engines;
- means for communicating the encrypted message to the bus endpoint via the security interconnect;
- and
- means for transmitting the encrypted message across the interconnect by the bus endpoint.
Dependencies are inferred from the claim text.