Method and apparatus for execution of neural network

A non-transitory computer-readable storage medium storing a set of instructions that is executable by at least one processing unit to cause the computer to perform a method, the processing unit comprising a command parser having circuitry configured to dispatch commands and computing tasks and at least one core communicatively coupled with the command parser and configured to process the dispatched computing task, each core comprising a convolution unit, a pooling unit, at least one operation unit and a sequencer communicatively coupled with the convolution unit, the pooling unit, and the at least one operation unit and having circuitry configured to distribute instructions of the dispatched computing task to the convolution unit, the pooling unit, and the at least one operation unit for execution, the sequencer further comprising circuitry configured to modify the instructions of the core;

• the method comprising:
• reading, by the convolution unit, data from a local memory of the at least one operation unit;
• performing, by the convolution unit, a convolution operation on the data to generate a feature map;
• and
• performing, by the pooling unit, a pooling operation on the feature map.

A processing unit, comprising:

• a command parser having circuitry configured to dispatch commands and computing tasks;
• and
• at least one core communicatively coupled with the command parser and configured to process the dispatched computing task, each core comprising:
• a convolution unit having circuitry configured, by a convolution instruction, to perform a convolution operation to generate a feature map;
• a pooling unit having circuitry configured, by a pooling instruction, to perform a pooling operation on the feature map;
• at least one operation unit having circuitry configured to process data;
• and
• a sequencer communicatively coupled with the convolution unit, the pooling unit, and the at least one operation unit, and having circuitry configured to distribute instructions of the dispatched computing task to the convolution unit, the pooling unit, and the at least one operation unit for execution;
• wherein the sequencer further comprises circuitry configured to modify the instructions of the core.