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US 11,768,798 B2Granted
Multi-level hierarchical routing matrices for pattern-recognition processors
AssigneeMicron Technology, Inc.
InventorsHarold B Noyes, David R. Brown
Life of this patent
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Abstract
Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.
Claims20
A state machine engine, comprising:
- a logical group comprising a plurality of route lines, a first feature cell, a second feature cell, and an output drive selector coupled to the first feature cell via a first non-programmable connection and coupled to the second feature cell via a second non-programmable connection, wherein the first feature cell and the second feature cell of the logical group are separate and distinct from any additional feature cells of any other logical group of the state machine engine, wherein the first feature cell comprises a data analysis element comprising a memory component configured to be programmed with configuration data, wherein the data analysis element is configured to analyze at least a portion of the data to be analyzed based on the configuration data and to output a result.
A state machine engine, comprising:
- a first logical group comprising a first plurality of route lines, a first feature cell, a second feature cell, and a first output drive selector coupled to the first feature cell via a first non-programmable connection and coupled to the second feature cell via a second non-programmable connection, wherein the first feature cell comprises a data analysis element comprising a memory component configured to be programmed with configuration data, wherein the data analysis element is configured to analyze at least a portion of the data to be analyzed based on the configuration data and to output a result;
- and
- a second logical group comprising a second plurality of route lines, a third feature cell, a fourth feature cell, and a second output drive selector coupled to the third feature cell via a third non-programmable connection and coupled to the fourth feature cell via a fourth non-programmable connection, wherein the first feature cell and the second feature cell of the first logical group are separate and distinct from the third feature cell and the fourth feature cell of the second logical group.
A finite state machine lattice, comprising:
- a plurality of blocks, wherein each block of the plurality of blocks comprises a plurality of rows, wherein each row of the plurality of rows comprises a plurality of logical groups, wherein each logical group comprises:
- a plurality of route lines;
- a first feature cell comprising a first data analysis element comprising a first plurality of memory cells configured to be programmed with first configuration data, wherein the first data analysis element is configured to analyze at least a portion of the data to be analyzed based on the first configuration data and to output a first result;
- a second feature cell comprising a second data analysis element comprising a second plurality of memory cells configured to be programmed with second configuration data, wherein the second data analysis element is configured to analyze at least a second portion of the data to be analyzed based on the second configuration data and to output a second result;
- and
- an output drive selector coupled to the first feature cell via a first non-programmable connection and coupled to the second feature cell via a second non-programmable connection, wherein the output drive selector is configured to transmit an output drive signal based upon a selection by the output drive selector.
3 more elements
Dependencies are inferred from the claim text.