US 11,768,794 B1Granted

Interface between processing unit and an external nonvolatile memory

AssigneeSilicon Laboratories Inc.

InventorsAslam Rafi, Thomas Saroshan David, Daniel Cooley

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Abstract

An interface between two devices is disclosed. To consume power, the signals used in the interface utilize CMOS signalling. Further, to achieve high speed, a reduced frequency clock is transmitted from one device to the second device. The second device has a clock multiplier to recreate the original clock. Both devices utilize a clock phase alignment block which aligns the phase of the clock with the incoming data. The clock phase alignment block utilizes a digital PLL to consume power. Further, since the digital PLL retains its state, the reduced frequency clock may be disabled when data is not being transmitted. This interface may be used to transmit serial data at rates up to and exceeding 2.5 Gbits/sec.

Claims19

Dependent claims

A system for providing a high speed interface between two devices, comprising:

a first device having an outgoing data signal, wherein the outgoing data signal is transmitted using a serdes clock, wherein the first device provides a reduced frequency clock, wherein a frequency of the reduced frequency clock is equal to a frequency of the serdes clock divided by an integer;
a second device to receive the outgoing data signal and the reduced frequency clock from the first device;
wherein the second device comprises:
a multiplier in communication with the reduced frequency clock to create a memory serdes clock having a frequency equal to the frequency of the serdes clock;
a data buffer to receive the outgoing data signal and create an incoming data signal;
a clock phase alignment block, which utilizes a digital PLL to align a phase of the memory serdes clock with the incoming data signal, wherein the clock phase alignment block comprises a delay line having the memory serdes clock as an input and having a plurality of outputs of different delays, and a sampler, having a plurality of storage elements, a number of storage elements equal to a number of the plurality of outputs of the delay line, wherein each of the plurality of outputs of the delay line are clocked into respective one of the plurality of storage elements of the sampler by a transition of the incoming data signal, wherein a delay through the delay line is greater than or equal to two periods of the memory serdes clock, such that, at each transition of the incoming data signal, the sampler captures at least two rising edges of the memory serdes clock;
and
a serial to parallel converter which clocks the incoming data signal using the memory serdes clock that has been phase aligned.

5 more elements

Dependencies are inferred from the claim text.