Apparatus and method for memory management in a graphics processing environment

A system, comprising:

• a host processor;
• a first memory interface to couple the host processor to a system memory;
• a plurality of graphics processing resources to execute instructions and process data;
• partitioning hardware logic to indicate partitioning of the plurality of graphics processing resources into a plurality of slices, each slice of the plurality of slices including a corresponding subset of the graphics processing resources to be allocated to a corresponding virtual machine (VM);
• a plurality of memory management circuits, each memory management circuit corresponding to a slice of the plurality of slices and configured to perform memory access operations including address translations, page fault operations, and page walk operations, each memory management circuit comprising:
• one or more translation lookaside buffers (TLBs), each TLB to store at least some mappings of guest virtual addresses (GVAs) to host physical addresses (HPAs) maintained in page tables in the system memory, wherein each GVA is associated with a particular VM;
• and
• an interface to couple the memory management circuit to a system-level memory management circuit, the interface to provide communication with the system-level memory management circuit to ensure coherency between mappings of GVAs to HPAs stored in the one or more TLBs and mappings of GVAs to HPAs stored in at least one TLB of the system-level memory management circuit.