Training and operations with a double buffered memory topology
AssigneeRambus Inc.
InventorsChi-Ming Yeung, Yoshie Nakabayashi, Thomas Giovannini, Henry Stracovsky
Life of this patent
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Abstract
System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).
Claims20
A method of operation of a memory controller, the method comprising:
- sending, with a first time delay, a write command from the memory controller to a driver coupled between the memory controller and a dual in-line memory module (DIMM), wherein the write command is configured to instruct the DIMM to store data;
- and
- sending, with a second time delay, a data buffer control signal from the memory controller to a data buffer coupled between the memory controller and the DIMM, the data buffer control signal to cause the data buffer to send the data to the DIMM, wherein sending the data buffer control signal to the data buffer at least partially overlaps in time with the sending of the write command to the driver.
A memory controller comprising:
- a command/address (CA) interface to couple to a CA bus, wherein the CA bus is further coupled to a driver coupled between the memory controller and a dual in-line memory module (DIMM), the CA interface to send, with a first time delay, a write command to the driver coupled between the memory controller and the DIMM, wherein the write command is configured to instruct the DIMM to store data;
- and
- a control interface to couple to a control bus, wherein the control bus is further coupled to a data buffer coupled between the memory controller and the DIMM, the control interface to send, with a second time delay, a data buffer control signal to the data buffer coupled between the memory controller and the DIMM, the data buffer control signal to cause the data buffer to send the data to the DIMM, wherein sending the data buffer control signal to the data buffer at least partially overlaps in time with the sending of the write command to the driver.
A method of operation of a memory controller, the method comprising:
- sending, with a first time delay, a write command from the memory controller to a driver coupled between the memory controller and a memory subsystem, wherein the write command is configured to instruct the memory subsystem to store data;
- and
- sending, with a second time delay, a data buffer control signal from the memory controller to a data buffer coupled between the memory controller and the memory subsystem, the data buffer control signal to cause the data buffer to send the data to the memory subsystem, wherein sending the data buffer control signal to the data buffer at least partially overlaps in time with the sending of the write command to the driver.
Dependencies are inferred from the claim text.