Non-volatile dual inline memory module (NVDIMM) for supporting DRAM cache mode and operation method of NVDIMM
AssigneeSamsung Electronics Co., Ltd.
InventorSunyoung Lim
Life of this patent
Estimating the term…
Abstract
Provided are a non-volatile dual inline memory module (NVDIMM) supporting a DRAM cache mode and an operation method of the NVDIMM. The NVDIMM includes a DRAM chip, an NVM chip, and a controller that controls the DRAM chip to operate as a cache memory of the NVM chip. The controller sends a read command to the DRAM chip with reference to a cache address of data requested to be written from a host to the NVM chip, and sends a write command to the NVM chip with reference to an address of the data requested to be written at a time point when a read latency (RL) of the DRAM chip and a write latency (WL) of the NVM chip coincide with each other.
Claims20
An operation method of a memory module comprising a non-volatile memory chip, a volatile memory chip, and a controller configured to control the volatile memory chip and the non-volatile memory chip such that the volatile memory chip operates as a cache memory of the non-volatile memory chip, the operation method comprising:
- receiving, by the controller, a write request from a host to the non-volatile memory chip;
- sending, by the controller, a first read command to the volatile memory chip with reference to a cache address of first data requested to be written to the non-volatile memory chip;
- sending, by the controller, a first write command to the non-volatile memory chip with reference to second data requested to be written;
- and
- configuring, by the controller, the first data output from the volatile memory chip in response to the first read command as second data, and controlling the second data to be written to the non-volatile memory chip,
- wherein the first write command is applied before the first data is output to first internal data lines by the first read command after the first read command is applied, and at a time point when a read latency of the first read command and a write latency of the first write command coincide with each other whereby the time point occurs after the read latency of the first read command and the write latency of the first write command elapse, the second data is written to the non-volatile memory chip.
An operation method of a memory module comprising a non-volatile memory chip, a volatile memory chip, and a controller configured to control the volatile memory chip and the non-volatile memory chip such that the volatile memory chip operates as a cache memory of the non-volatile memory chip, the operation method comprising:
- receiving, by the controller, a read request from a host to the non-volatile memory chip;
- sending, by the controller, a first read command to the non-volatile memory chip with reference to a cache address of data requested to be read from the non-volatile memory chip;
- sending, by the controller, a first write command to the volatile memory chip with reference to the first data requested to be read;
- and
- configuring, by the controller, second data output from the non-volatile memory chip in response to the first read command as first data related with the first write command, and controlling the first data to be written to the volatile memory chip,
- wherein the first write command is applied before the second data is output to second internal data lines of the memory module by the first read command after the first read command is applied, and
- at a time point when a read latency of the first read command and a write latency of the first write command coincide with each other whereby the time point occurs after the read latency of the first read command and the write latency of the first write command elapse, the first data is written to the volatile memory chip.
An operation method of a memory module comprising a non-volatile memory chip, a volatile memory chip, and a controller, the operation method comprising:
- sending, by the controller, a first command related to first data of the volatile memory chip to the volatile memory chip at a first time;
- sending, by the controller, a second command related to second data of the non-volatile memory chip before the first data is output at a second time;
- moving the first data from the volatile memory chip to the non-volatile memory chip at a time point when a first latency of the first command and a second latency of the second command coincide with each other whereby the time point occurs after latencies of the first command and the second command elapse, wherein the first data is configured by the controller at the time point as a first data chunk of a plurality of data chunks in a cache flush operation;
- and
- moving the second data from the non-volatile memory chip to the volatile memory chip at the time point, wherein the second data is configured by the controller at the time point as the first data chunk of the plurality of data chunks in a cache fill operation.
Dependencies are inferred from the claim text.