Cache memory addressing

An apparatus comprising:

• an interface configured to couple to multiple wires of an inter-chip interconnect for a memory device;
• and
• logic coupled to the interface and configured to:
• transmit a first message for a memory request to a cache memory over the multiple wires of the inter-chip interconnect, the memory request related to a memory address including a most significant bit (MSB) portion and a least significant bit (LSB) portion, the first message including the LSB portion of the memory address;
• and
• after transmission of the first message, transmit a second message for the memory request to the cache memory over the multiple wires of the inter-chip interconnect, the second message including the MSB portion of the memory address.

An apparatus comprising:

• an interface configured to couple to multiple wires of an inter-chip interconnect;
• a cache memory;
• and
• logic coupled to the interface and the cache memory, the logic configured to:
• receive via the interface a least significant bit (LSB) portion of a memory address from the multiple wires of the inter-chip interconnect;
• start indexing into the cache memory using the LSB portion of the memory address prior to reception of a most significant bit (MSB) portion of the memory address;
• and
• receive via the interface the MSB portion of the memory address from the multiple wires of the inter-chip interconnect after the indexing is started.