Uniform memory access in a system having a plurality of nodes

A system, comprising:

• a plurality of nodes, each respective node of the plurality of nodes including a respective processing unit and a respective memory unit, the respective memory unit including a respective first interface to interface with the respective processing unit and a respective second interface to interface with one or more memory units in one or more other nodes of the plurality of nodes;
• and
• memory access paths, wherein each of the memory access paths is between the second interface of one memory unit in one node and the second interface of another memory unit in another node, wherein none of the memory access paths go through any of the processing unit in any of the plurality of nodes;
• and
• wherein the respective memory unit in the respective node of the plurality of nodes includes a node control device configurable to:
• receive a memory access request from the respective processing unit via the respective first interface;
• in response to the memory access request including a first address in a local unified memory access (UMA) address space accessible by applications running on the respective processing unit, translate the first address to a second address in a global UMA address space, the global UMA address space being mapped to a physical UMA address space including physical address spaces associated with memory units in the plurality of nodes;
• and
• transmit a first request packet via the second interface, the first request packet including the second address or a first target address for a first target node among the plurality of nodes.