Post error correction code registers for cache metadata
AssigneeMicron Technology, Inc.
InventorsTaeksang Song, Saira Samar Malik, Chinnakrishnan Ballapuram
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Abstract
Methods, systems, and devices for post error correction code (ECC) registers for cache metadata are described. A device may read metadata from a memory array included in the device. The metadata may include information for operating a volatile memory as a cache for a non-volatile memory. The device may perform an ECC operation on the metadata based on reading the metadata from the memory array. After performing the ECC operation on the metadata, the device may write the metadata to a register that is coupled with the memory array. The device may then write the metadata from the register to the memory array.
Claims25
An apparatus, comprising:
- a non-volatile memory;
- a volatile memory;
- and
- an interface controller coupled with the non-volatile memory and the volatile memory, the interface controller operable to cause the apparatus to:
- read metadata from a volatile memory array included in the interface controller, the metadata associated with operating the volatile memory as a cache for the non-volatile memory;
- perform an error correction code (ECC) decoding operation on the metadata based at least in part on reading the metadata from the volatile memory array;
- write, based at least in part on performing the ECC decoding operation, the metadata or corrected metadata to a register that is coupled with the volatile memory array;
- and
- write the metadata or the corrected metadata from the register to the volatile memory array.
A method, comprising:
- reading metadata from a volatile memory array included in an interface controller coupled with volatile memory and a non-volatile memory, the metadata associated with operating the volatile memory as a cache for the non-volatile memory;
- performing an error correction code (ECC) decoding operation on the metadata based at least in part on reading the metadata from the volatile memory array;
- writing, based at least in part on performing the ECC decoding operation, the metadata or corrected metadata to a register that is coupled with the volatile memory array;
- and
- writing the metadata or the corrected metadata from the register to the volatile memory array.
An apparatus, comprising:
- a non-volatile memory;
- a volatile memory configured to operate as a cache for the non-volatile memory;
- and
- an interface controller coupled with the non-volatile memory and the volatile memory, the interface controller comprising:
- a static random access memory (SRAM) array configured to store metadata associated with operating the volatile memory as the cache;
- error correction code (ECC) logic coupled with the SRAM array and configured to perform an ECC decoding operation on the metadata from the SRAM array;
- and
- a register, for a bank of the volatile memory, coupled with the ECC logic and configured to store metadata or corrected metadata from the ECC logic, wherein the interface controller is configured to update the metadata or the corrected metadata in the register and communicate the metadata or the corrected metadata from the register to the SRAM array.
Dependencies are inferred from the claim text.