System and method for transparent register data error detection and correction via a communication bus
AssigneeInfineon Technologies AG
InventorsHeimo Hartlieb, Christian Heiling
Life of this patent
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AssigneeInfineon Technologies AG
InventorsHeimo Hartlieb, Christian Heiling
Estimating the term…
A method includes detecting in a communication bus a write command to a first circuit and comparing a write address of the write command with a set of safe addresses. When the write address matches a safe address of the set of safe addresses, an error correction code (ECC) is generated based at least on write data of the write command, and the ECC is stored in a memory of a parameter safe storage circuit. A read command to the first circuit is detected in the communication bus, a read address of the read command is compared with the set of safe addresses, and, when the read address matches a safe address of the set of safe addresses, it is determined whether read data of the read command is corrupted based on the stored ECC, and an error notification is provided when the read data is determined to be corrupted.
A method comprising:
An integrated circuit comprising:
A parameter safe storage circuit comprising a memory, the parameter safe storage circuit configured to be coupled to a communication bus and to:
Dependencies are inferred from the claim text.