Processing device

A processing device for performing parallel processing by a plurality of cores, and performing an inter-core communication of a plurality of communication systems that are distinguished as separate communications by the plurality of cores, the processing device comprising:

• a shared memory that is accessible by the plurality of cores at the same time and is provided with a plurality of buffer units that can be used for the inter-core communication;
• a transmission core that writes data to the buffer unit in the inter-core communication via the shared memory;
• and
• a reception core that reads data from the buffer unit in the inter-core communication,
• wherein, when transmitting data by the inter-core communication, the transmission core stores the data and a counter value updated according to a writing order to the buffer unit determined by a counter value managed for each of the communication systems respectively stored in the plurality of buffer units, and
• wherein, when receiving data in the inter-core communication, the reception core reads data from a buffer unit in which latest data of each of the communication systems, which is determined by the counter value stored in each of the plurality of buffer units.