US 11,768,714 B2Granted

On-chip hardware semaphore array supporting multiple conditionals

AssigneeMicrosoft Technology Licensing, LLC

InventorsXiaoling Xu, Timothy Hume Heil, Deepak Goel

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Abstract

Hardware semaphores are utilized to increase the speed with which preconditions are evaluated. On an individual basis, each hardware semaphore can implement a binary semaphore or a counting semaphore. Collections of hardware semaphores can be chained together to implement a chain semaphore that can support multiple conditionals. In addition, hardware semaphores can have the capability, not only of generating an interrupt, but, in addition, being able to generate commands, such as to other semaphores. The implementation of a chain semaphore spanning multiple hardware semaphores can be performed by a compiler at compile time or at run time. An integrated circuit chip can comprise multiple execution units, such as processing cores, and individual ones of the execution units can be associated with multiple hardware semaphores, such as in the form of hardware semaphore arrays. A dedicated network-on-chip enables hardware semaphore communication.

Claims20

Dependent claims

A method of utilizing multiple hardware semaphore circuitry as a chain semaphore, the method comprising:

receiving computer-executable instructions specifying a multiple conditional dependency for a first consumer process, the multiple conditional dependency enumerating states of outputs of multiple producer processes which are to be met in order for the first consumer process to execute properly;
setting a first hardware semaphore circuitry as a first semaphore in the chain semaphore to:
maintain a first state machine such that generation of output by a first producer process changes the first state machine, the first producer process being one of the multiple producer processes;
and
generate a first condition met notification to a subsequent semaphore in the chain semaphore when the first state machine is in a state corresponding to a first condition specified by the multiple conditional dependency;
and
setting a second hardware semaphore circuitry as the subsequent semaphore in the chain semaphore to:
maintain a second state machine such that generation of output by a second producer process changes the second state machine, the second producer process being another one of the multiple producer processes;
and
generate a second condition met notification when the second state machine is in a state corresponding to:
(1) a second condition specified by the multiple conditional dependency and (2) all preceding semaphores in the chain semaphore having generated condition met notifications.

8 more elements

An integrated circuit chip comprising:

a first execution unit circuitry;
a second execution unit circuitry;
a first array of hardware semaphore circuitry associated with the first execution unit circuitry;
a second array of hardware semaphore circuitry associated with the second execution unit circuitry;
a first hardware semaphore circuitry that is set as a first semaphore in a chain semaphore, the first hardware semaphore circuitry:
maintaining a first state machine such that generation of output by a first producer process changes the first state machine;
and
generating a first condition met notification to a subsequent semaphore in the chain semaphore when the first state machine is in a state corresponding to a first condition of a multiple conditional dependency;
and
a second hardware semaphore circuitry that is set as the subsequent semaphore in the chain semaphore, the second hardware semaphore circuitry:
maintaining a second state machine such that generation of output by a second producer process changes the second state machine;
and
generating a second condition met notification when the second state machine is in a state corresponding to:
(1) a second condition specified by the multiple conditional dependency and (2) all preceding semaphores in the chain semaphore having generated condition met notifications.

11 more elements

An integrated circuit chip comprising:

multiple block circuitries, each block circuitry comprising:
an execution unit circuitry;
and
an array of two or more hardware semaphore circuitries;
and
a dedicated network-on-chip (NOC) circuitry communicationally coupling the multiple block circuitries;
wherein at least one block circuitry, of the multiple block circuitries, comprises:
a first hardware semaphore circuitry that is set as a first semaphore in a chain semaphore, the first hardware semaphore circuitry:
maintaining a first state machine such that generation of output by a first producer process changes the first state machine;
and
generating a first condition met notification to a subsequent semaphore in the chain semaphore when the first state machine is in a state corresponding to a first condition of a multiple conditional dependency;
and
a second hardware semaphore circuitry that is set as the subsequent semaphore in the chain semaphore, the second hardware semaphore circuitry:
maintaining a second state machine such that generation of output by a second producer process changes the second state machine;
and
generating a second condition met notification when the second state machine is in a state corresponding to:
(1) a second condition specified by the multiple conditional dependency and (2) all preceding semaphores in the chain semaphore having generated condition met notifications.

14 more elements

Dependencies are inferred from the claim text.