Processing device with vector transformation execution
AssigneeTexas Instruments Incorporated
InventorsMujibur Rahman, Timothy David Anderson, Joseph Zbiciak
Life of this patent
Estimating the term…
Abstract
An integrated circuit, comprising an instruction pipeline that includes instruction fetch phase circuitry, instruction decode phase circuitry, and instruction execution circuitry. The instruction execution circuitry includes transformation circuitry for receiving an interleaved dual vector operand as an input and for outputting a first natural order vector including a first set of data values from the interleaved dual vector operand and a second natural order vector including a second set of data values from the interleaved dual vector operand.
Claims20
A processor, comprising:
- a multiplication unit configured to:
- receive vector data;
- perform multiplication on the vector data;
- and
- generate an output vector based on the performed multiplication;
- and
- a transformation unit configured to:
- receive the vector data;
- rearrange words from the vector data into a transformed vector;
- and
- output the transformed vector.
A circuit, comprising:
- a controller;
- a selector including a first input, a second input, and a selector output;
- a multiplication circuit including a plurality of multiplication inputs coupled to the selector output, wherein the multiplication circuit further includes a plurality of multiplication outputs, and wherein the multiplication circuit further includes a control input coupled to the controller;
- and
- a transformation circuit including a transformation input coupled to the selector output,
- wherein the transformation circuit further includes a transformation output,
- wherein the transformation circuit further includes a control input coupled to the controller, and
- wherein the transformation circuit includes a lower even half transformation circuit and a lower odd half transformation circuit.
Dependencies are inferred from the claim text.