Compaction of architected registers in a simultaneous multithreading processor

A processor having one or more processor cores, the one or more processor cores comprising:

• a first superslice comprising a first hardware thread, a third hardware thread, and a first slice target register file (STF) having a first set of STF blocks;
• and
• a second superslice comprising a second hardware thread, a fourth hardware thread, and a second STF having a second set of STF blocks,
• wherein the processor is configured to perform a method comprising:
• receiving an instruction to reconfigure the processor from a first simultaneous multithreading (SMT) mode to a second SMT mode, wherein the second SMT mode includes fewer threads than the first SMT mode;
• deactivating, in response to switching from the first SMT mode to the second SMT mode, the third and fourth hardware threads;
• allocating a first set of entries of the first STF to the first hardware thread;
• allocating a second set of entries of the second STF to the second hardware thread;
• compacting STF data for the first hardware thread into the first set of entries of the first STF;
• and
• compacting STF data for the second hardware thread into the second set of entries of the second STF,
• wherein the allocating the first set of entries, the allocating the second set of entries, the compacting the STF data for the first hardware thread, and the compacting the STF data for the second hardware thread are performed in response to receiving the instruction.

A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising:

• receiving a particular instruction to reconfigure a processor core from a first simultaneous multithreading (SMT) mode to a second SMT mode, wherein the second SMT mode includes fewer threads than the first SMT mode;
• allocating a first set of entries in a first register file to a first hardware thread of the processor core;
• allocating a second set of entries in a second register file to a second hardware thread of the processor core;
• and
• compacting register data in the first and second register files, wherein register data associated with the first hardware thread is compacted into the first set of entries, and register data associated with the second hardware thread is compacted into the second set of entries,
• wherein the allocating the first set of entries, the allocating the second set of entries, and the compacting are performed in response to receiving the particular instruction.