Instruction and logic for tracking fetch performance bottlenecks
AssigneeIntel Corporation
InventorAhmad Yasin
Life of this patent
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Abstract
A processor includes a front end, an execution unit, a retirement stage, a counter, and a performance monitoring unit. The front end includes logic to receive an event instruction to enable supervision of a front end event that will delay execution of instructions. The execution unit includes logic to set a register with parameters for supervision of the front end event. The front end further includes logic to receive a candidate instruction and match the candidate instruction to the front end event. The counter includes logic to generate the front end event upon retirement of the candidate instruction.
Claims24
A processor comprising:
- front end circuitry comprising fetch circuitry to fetch an instruction and decode circuitry to decode the fetched instruction into a set of one or more micro-operations;
- execution circuitry to execute the set of one or more micro-operations;
- retirement circuitry to retire the instruction after execution;
- performance monitoring circuitry to capture event based sampling data, for one or more front end events, only for retired instructions;
- and
- a model specific register comprising a field to identify the one or more front end events that are to be tracked.
A processor comprising:
- front end circuitry comprising fetch circuitry to fetch an instruction and decode circuitry to decode the fetched instruction into a set of one or more micro-operations;
- execution circuitry to execute the set of one or more micro-operations;
- a reorder buffer to track out-of-order execution of instructions;
- retirement circuitry to retire the instruction from the reorder buffer;
- performance monitoring circuitry to capture event based sampling data, for one or more front end events, only for instructions retired by the retirement circuitry;
- and
- a model specific register comprising a field to identify the one or more front end events that are to be tracked.
A method comprising:
- setting a field in a model specific register of a processor to cause one or more front end events to be tracked by performance monitoring circuitry of the processor;
- fetching an instruction by fetch circuitry of front end circuitry of the processor;
- decoding the fetched instruction, by decode circuitry of the front end circuitry of the processor, into a set of one or more micro-operations;
- executing the set of one or more micro-operations by execution circuitry of the processor;
- retiring the instruction after execution by retirement circuitry of the processor;
- and
- capturing event based sampling data by the performance monitoring circuitry, for the one or more front end events, only for retired instructions.
Dependencies are inferred from the claim text.