Apparatus and method for vector multiply and accumulate of packed bytes

A method comprising:

• decoding an instruction, the instruction comprising fields to identify a first operand to indicate a first plurality of packed bytes, a second operand to indicate a second plurality of packed bytes, and a third operand to indicate a plurality of packed doublewords, the instruction further comprising an opcode to indicate whether bytes in the first plurality of packed bytes are signed and whether bytes in the second plurality of packed bytes are signed;
• and
• executing the instruction by:
• sign-extending or zero-extending first and second plurality of packed bytes from first and second source registers based on the opcode to generate a first and second plurality of words corresponding to the first and second plurality of packed bytes;
• multiplying each of the first plurality of words with a corresponding one of the second plurality of words to generate multiple sets of temporary products, each set comprising four temporary products;
• adding the four temporary products in each set to generate a plurality of temporary sums, each of the temporary sums corresponding to a different set of the temporary products and to a doubleword location in a third source register;
• accumulating each of the plurality of temporary sums with a respective packed doubleword value from the corresponding doubleword location in a third source register to generate a plurality of accumulated doubleword results;
• and
• storing each of the plurality of accumulated doubleword results in the corresponding doubleword location in a destination register.

An article of manufacture having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:

• decoding an instruction, the instruction comprising fields to identify a first operand to indicate a first plurality of packed bytes, a second operand to indicate a second plurality of packed bytes, and a third operand to indicate a plurality of packed doublewords, the instruction further comprising an opcode to indicate whether bytes in the first plurality of packed bytes are signed and whether bytes in the second plurality of packed bytes are signed;
• and
• executing the decoded instruction by:
• sign-extending or zero-extending first and second plurality of packed bytes from first and second source registers based on the opcode to generate a first and second plurality of words corresponding to the first and second plurality of packed bytes;
• multiplying each of the first plurality of words with a corresponding one of the second plurality of words to generate multiple sets of temporary products, each set comprising four temporary products;
• adding the four temporary products in each set to generate a plurality of temporary sums, each of the temporary sums corresponding to a different set of the temporary products and to a doubleword location in a third source register;
• accumulating each of the plurality of temporary sums with a respective packed doubleword value from the corresponding doubleword location in a third source register to generate a plurality of accumulated doubleword results;
• and
• storing each of the plurality of accumulated doubleword results in the corresponding doubleword location in a destination register.