US 11,768,663 B1Granted

Compaction of multiplier and adder circuits

AssigneeXilinx, Inc.

InventorsSrijan Tiwary, Aman Gayasen

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Abstract

Approaches for logic compaction include inputting an optimization directive that specifies one of area optimization or speed optimization to a synthesis tool executing on a computer processor. The synthesis tool identifies a multiplier and/or an adder specified in a circuit design and synthesizing the multiplier into logic having LUT-to-LUT connections between LUTs on separate slices of a programmable integrated circuit (IC) in response to the optimization directive specifying speed optimization. The synthesis tool synthesizes the multiplier and/or adder into logic having LUT-carry connections between LUTs and carry logic within a single slice of the programmable IC in response to the optimization directive specifying area optimization. The method includes implementing a circuit on the programmable IC from the logic having LUT-carry connections in response to the optimization directive specifying area optimization.

Claims20

Dependent claims

A method comprising:

inputting an optimization directive that specifies one of area optimization or speed optimization to a synthesis tool executing on a computer processor;
identifying by the synthesis tool, a multiplier of a first factor and a second factor specified in a circuit design;
synthesizing the multiplier by the synthesis tool into logic having LUT-to-LUT connections between LUTs on separate slices of a programmable integrated circuit (IC) in response to the optimization directive specifying speed optimization, wherein a LUT is a look-up table;
and
synthesizing the multiplier by the synthesis tool into logic having LUT-carry connections between LUTs and carry logic within a single slice of the programmable IC in response to the optimization directive specifying area optimization, wherein synthesizing the multiplier into logic having LUT-carry connections includes generating, for each pair of a plurality of pairs of partial products of the first factor and the second factor, logic that produces an intermediate sum of the pair on a plurality of LUTs and carry logic in a respective slice of the programmable IC.

2 more elements

A system comprising:

one or more processors;
a memory arrangement configured with instructions of a synthesis tool that when executed by the one or more processors cause the one or more processors to perform operations including:
inputting an optimization directive that specifies one of area optimization or speed optimization;
identifying a multiplier of a first factor and a second factor specified in a circuit design;
synthesizing the multiplier into logic having LUT-to-LUT connections between LUTs on separate slices of a programmable integrated circuit (IC) in response to the optimization directive specifying speed optimization, wherein a LUT is a look-up table;
and
synthesizing the multiplier into logic having LUT-carry connections between LUTs and carry logic within a single slice of the programmable IC in response to the optimization directive specifying area optimization, wherein synthesizing the multiplier into logic having LUT-carry connections includes generating, for each pair of a plurality of pairs of partial products of the first factor and the second factor, logic that produces an intermediate sum of the pair on a plurality of LUTs and carry logic in a respective slice of the programmable IC.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/014,410Filed 8 Sep 2020
Granted: 26 Sep 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 7/5334
Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even: by using multiple bit scanning, i.e. by…
G06F 7/506
In bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination: with simultaneous carry generation for, or…
G06F 7/57
Using non-contact-making devices, e.g. tube, solid state device; using unspecified devices: arithmetic logic units [ALU], i.e. arrangements or…
G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist