Efficient logic blocks architectures for dense mapping of multipliers
AssigneeIntel Corporation
InventorsSadegh Yazdanshenas, Tim Vanderhoek
Life of this patent
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Abstract
An integrated circuit includes a logic block configured to perform multiplication operations. The logic block includes a plurality of lookup tables configured to receive a plurality of inputs and generate a first plurality of outputs. Additionally, the logic block includes adding circuitry configured to receive the first plurality of outputs and generate a second plurality of outputs. Furthermore, the logic block includes circuitry configured to receive a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs.
Claims20
An integrated circuit, comprising a logic block configurable to perform multiplication operations, wherein the logic block comprises:
- a plurality of lookup tables configurable to receive a plurality of inputs and generate a first plurality of outputs, wherein a first portion of the plurality of lookup tables is configurable to receive a first bit value of the plurality of inputs;
- a multiplexer communicatively coupled to a second portion of the plurality of lookup tables that is different than the first portion of the plurality of lookup tables, wherein the multiplexer is configurable to:
- receive the first bit value of the plurality of inputs, a second bit value of the plurality of inputs, and a control signal;
- and
- provide either the first bit value or the second bit value to the second portion of the plurality of lookup tables based on the control signal;
- adding circuitry configurable to receive the first plurality of outputs and generate a second plurality of outputs;
- and
- circuitry configurable to receive a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs.
A logic block implementable on a programmable logic device, the logic block comprising:
- a plurality of lookup tables configurable to receive a plurality of inputs and generate a first plurality of outputs, wherein a first portion of the plurality of lookup tables is configurable to receive a first bit value of the plurality of inputs;
- a multiplexer communicatively coupled to a second portion of the plurality of lookup tables that is different than the first portion of the plurality of lookup tables, wherein the multiplexer is configurable to:
- receive the first bit value of the plurality of inputs, a second bit value of the plurality of inputs, and a control signal;
- and
- provide either the first bit value or the second bit value to the second portion of the plurality of lookup tables based on the control signal;
- adding circuitry configurable to receive the first plurality of outputs and generate a second plurality of outputs;
- and
- circuitry configurable to receive a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs.
An integrated circuit device, comprising a plurality of logic blocks, wherein each logic block of the plurality of logic blocks comprises:
- a plurality of lookup tables configurable to receive a plurality of inputs and generate a first plurality of outputs, wherein a first portion of the plurality of lookup tables is configurable to receive a first bit value of the plurality of inputs;
- a multiplexer communicatively coupled to a second portion of the plurality of lookup tables that is different than the first portion of the plurality of lookup tables, wherein the multiplexer is configurable to:
- receive the first bit value of the plurality of inputs, a second bit value of the plurality of inputs, and a control signal;
- and
- provide either the first bit value or the second bit value to the second portion of the plurality of lookup tables based on the control signal;
- adding circuitry configurable to receive the first plurality of outputs and generate a second plurality of outputs;
- and
- circuitry configurable to receive at least a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs.
Dependencies are inferred from the claim text.