Look ahead normaliser

A method comprising:

• in a first hardware logic stage:
• in a plurality of OR-reducing operations, performing OR-reduction on a different subset of bits from an input number with a plurality of OR-reduction logic elements;
• shifting the input number dependent upon a value output by a first of the OR-reducing operations to generate a first updated binary number;
• and
• outputting the first updated binary number to a next hardware logic stage;
• in one or more intermediate hardware logic stages:
• in a plurality of OR-reducing operations, performing OR-reduction on a different subset of bits from an updated binary number received from an immediately previous hardware logic stage with a plurality of OR-reduction logic elements;
• selecting one of a plurality of OR-reduction results received from a previous hardware logic stage with one or more multiplexers;
• shifting the updated binary number received from an immediately previous hardware logic stage dependent upon the selected OR-reduction result to generate an intermediate updated binary number;
• and
• outputting the intermediate updated binary number to a next hardware logic stage;
• and
• in a final hardware logic stage:
• selecting one of a plurality of OR-reduction results received from a previous hardware logic stage with one or more multiplexers;
• shifting the updated binary number received from an immediately previous hardware logic stage dependent upon the selected OR-reduction result to generate a final updated binary number;
• and
• outputting the final updated binary number, wherein, for the final hardware logic stage, the final updated binary number output by the hardware logic stage is the normalised input number.

A non-transitory computer readable storage medium having stored thereon a computer readable dataset description, which when processed in an integrated circuit manufacturing system, causes the system to generate a processor comprising hardware logic arranged to normalise an n-bit input number, the hardware logic comprising:

• a first hardware logic stage comprising a plurality of OR-reduction logic elements and arranged to output a first updated binary number, wherein each OR-reduction logic element is arranged to perform OR-reduction on a different subset of bits from the input number, the first updated binary number comprising a shifted version of the input number, the shifting dependent upon a value output by a first of the OR-reduction elements;
• one or more intermediate hardware logic stages, each arranged to output an intermediate updated binary number and comprising a plurality of OR-reduction logic elements and one or more multiplexers, wherein each OR-reduction logic element in an intermediate stage is arranged to perform OR-reduction on a different subset of bits from an updated binary number received from an immediately previous hardware logic stage and a first of the multiplexers is arranged to select one of a plurality of OR-reduction results received from a previous hardware logic stage, the intermediate updated binary number comprising a shifted version of the updated binary number received from an immediately previous hardware logic stage, the shifting dependent upon the selected OR-reduction result;
• and
• a final hardware logic stage, comprising one or more multiplexers and arranged to output a final updated binary number, wherein a first of the multiplexers is arranged to select one of a plurality of OR-reduction results received from a previous hardware logic stage, the final updated binary number comprising a shifted version of the updated binary number received from an immediately previous hardware logic stage, the shifting dependent upon the selected OR-reduction result.