Flash controller for ASIC and control method therefor

A FLASH controller for ASIC, comprising a main control module, and an arbitration module, a read data fifo, and a write data fifo connected with the main control module, wherein the read data fifo and the write data fifo are both connected with the arbitration module and a data interface module, and the data interface module is connected with an AHB data bus;

• the FLASH controller further comprises a register module, wherein the register module is connected with the read data fifo, the write data fifo, the arbitration module, and a configuration interface module;
• the configuration interface module is connected with an AHB configuration bus;
• the main control module is connected with the register module through a synchronization module;
• and
• the main control module comprises a data transmitter sub-module used to send FLASH data information, a data receiver sub-module used to acquire data from a FLASH interface, and a clock generator sub-module for clock generation, wherein
• the clock generator sub-module comprises a TX clock generation branch, and the generated TX clock is used as the working clock of a FLASH device;
• the TX clock generation branch comprises a first frequency division module and a first clock bypass selector connected with the output end of the frequency division module, and the first clock bypass selector is further connected with a TX clock gating module, and an output of the TX clock gating module is input to the first clock bypass selector which outputs the TX clock;
• the clock generator sub-module further comprises an RX clock generation branch, and the generated RX clock is used as an internal data acquisition clock;
• and
• the RX clock generation branch comprises a first RX clock gating module and a second RX clock gating module wherein a phase difference between output signals of the first RX clock gating module and the second RX clock gating module is a master clock period.