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US 11,768,600 B2Granted
Computing reduction and prefix sum operations in memory
AssigneeMicron Technology, Inc.
InventorJeremiah J. Willcock
Life of this patent
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Abstract
The present disclosure includes apparatuses and methods for computing reduction and prefix sum operations in memory. A number of embodiments include processing circuitry configured to compute a reduction operation on data stored in a group of memory cells by splitting the data into a plurality of elements, copying each of the plurality of elements into elements that are wider than before being copied, and performing a logical operation associated with the reduction operation on each of the copied elements.
Claims20
An apparatus, comprising:
- processing circuitry configured to compute a reduction operation on data stored in a group of memory cells, wherein the reduction operation includes:
- splitting the data into even indexed elements and odd indexed elements;
- copying each of the even indexed elements and each of the odd indexed elements into elements twice as wide and half as tall as before being copied;
- performing an addition operation on each of the copied even indexed elements and each of the copied odd indexed elements;
- and
- performing an additional addition operation on data obtained by performing the addition operation on each of the copied even indexed elements and each of the copied odd indexed elements.
3 more elements
A method of operating processing circuitry, comprising:
- computing a reduction operation on data stored in a group of memory cells, wherein the reduction operation includes:
- splitting the data into even indexed elements and odd indexed elements;
- copying each of the even indexed elements and each of the odd indexed elements into elements twice as wide and half as tall as before being copied by copying each of the even indexed elements and each of the odd indexed elements into two by two elements;
- and
- performing an addition operation on each of the copied even indexed elements and each of the copied odd indexed elements.
2 more elements
An apparatus, comprising:
- processing circuitry configured to compute a reduction operation on data stored in a group of memory cells, wherein the reduction operation includes:
- splitting the data into even indexed elements and odd indexed elements;
- copying each of the even indexed elements and each of the odd indexed elements into elements twice as wide and half as tall as before being copied;
- and
- performing an addition operation on each of the copied even indexed elements and each of the copied odd indexed elements, wherein performing the addition operation includes adding each respective one of the copied even indexed elements to a different respective one of the copied odd indexed elements.
2 more elements
Dependencies are inferred from the claim text.