Systems and methods for multi-phase clock generation

A method of generating a set of multi-phase clock signals, comprising:

• performing phase error correction, by a phase error corrector, based on N intermediate signals to generate N clock output signals, wherein a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, wherein performing the phase error correction reduces phase errors among the clock output signals using a feedback signal received by the phase error corrector;
• and
• generating the feedback signal based on detected phase errors among the clock output signals.

A quadrature clock generator configured to generate four clock output signals evenly spaced by phase, comprising:

• a phase error corrector configured to receive four intermediate signals and to generate four clock output signals, wherein a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 90 degrees, the phase error corrector being further configured to receive a feedback signal and to reduce phase errors among the clock output signals based on the feedback signal;
• and
• a phase error detector configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.