Optimal timer array
AssigneepSemi Corporation
InventorGerald Alcorn
Life of this patent
Estimating the term…
Abstract
Methods and apparatuses for an optimal timer array using a single reference counter are presented. According to one aspect, timers of the timer array use the single reference counter to process different timed trigger requests. A count translation logic block translates counts corresponding to the requested timed triggers to target values of the reference counter. Register arrays that include the target values and active/inactive status flags of the timers are used to implement specific timers. Comparators are used to compare values of the reference counter to the target values to establish expiration of the requested timed triggers. A target translation logic block translates a current value of the reference counter to an offset value from the target values for monitoring by an external circuit.
Claims20
A radio frequency (RF) device, comprising:
- an RF circuit configured to process an RF signal;
- and
- a digital circuit configured to communicate with a master device separate from the RF device, the digital circuit comprising:
- a timer array configured to generate a plurality of timed triggers for synchronization of events between the master device and the RF circuit, the timer array comprising:
- an array of a plurality of target registers configured to store respective target offset values of the plurality of timed triggers;
- a reference counter operating from a reference clock;
- a count translation logic block that is configured to translate a number of reference clock counts corresponding to each timed trigger of the plurality of timed triggers to a target offset value of the reference counter;
- and
- a set valid flag logic block that is configured to:
- set a valid flag based on the time of request of the timed trigger, and
- reset the valid flag based on a time of completion of the timed trigger.
A radio frequency (RF) device, comprising:
- an RF circuit configured to process an RF signal;
- and
- a digital circuit configured to communicate with a master device separate from the RF device, the digital circuit comprising:
- a timer array configured to generate a plurality of timed triggers for synchronization of events between the master device and the RF circuit, the timer array comprising:
- a reference counter operating from a reference clock;
- a count translation logic block that is configured to translate a number of reference clock counts corresponding to each timed trigger of the plurality of timed triggers to a target offset value of the reference counter;
- wherein:
- the reference counter is free running, and
- the time of request of a first timed trigger of the plurality of timed triggers is different from the time of request of a second timed trigger of the plurality of timed triggers.
A digital circuit, comprising:
- a timer array configured to generate a plurality of timed triggers, the timer array comprising:
- a reference counter operating from a reference clock;
- and
- a count translation logic block that is configured to translate a number of reference clock counts corresponding to each timed trigger of the plurality of timed triggers to a target offset value of the reference counter;
- an array of a plurality of target registers configured to store respective target offset values of the plurality of timed triggers;
- a set valid flag logic block that is configured to:
- set a valid flag indicative of a requested timed trigger, and
- reset the valid flag indicative of completion of the requested timed trigger;
- an array of a plurality of valid flag registers configured to store respective valid flag values of the plurality of timed triggers;
- and
- an array of a plurality of comparators configured to compare a current value of the reference counter to the respective target offset values of the plurality of timed triggers.
A method for generating a timed trigger event, the method comprising:
- providing a reference counter operating from a reference clock;
- establishing a plurality of timers by assigning to each timer a target offset register, a set valid flag register, and a comparator;
- translating a requested timed trigger event into a target offset value of the reference counter and storing the target offset value to the target offset register of a respective timer of the plurality timers;
- setting a valid flag indicative of the requested timed trigger event and storing a value of the valid flag to the set valid flag register of the respective timer;
- based on the translating and the setting, comparing via a comparator of the respective timer a current value of the reference counter to the target offset value;
- and
- based on the comparing, generating the requested timed trigger event when the current value is equal to the target offset value.
Dependencies are inferred from the claim text.