Method and apparatus for timing-annotated scan-chain testing using parallel testbench

Testing apparatus for testing an integrated circuit device that operates at a clock frequency and that has at least one scan chain that includes a plurality of registers separated by combinatorial logic, the testing apparatus comprising:

• a test pattern generator configured to establish a respective scan chain test pattern for testing the at least one scan chain, the scan chain test pattern including a respective bit for each register in the plurality of registers of the scan chain;
• a timing module configured to determine in advance a respective timing delay for each pair of adjacent registers in the at least one scan chain;
• and
• a test signal module configured to, within a single clock period of the clock frequency, apply in parallel each bit of the respective scan chain pattern to a respective register in the plurality of registers in the at least one scan chain, each bit of the respective scan chain pattern being applied to its respective register at a respective temporal offset, within the single clock period, based on the respective timing delay.